#ifndef __DW_AHBDMA_H
#define __DW_AHBDMA_H

#include "t100.h"
#include "ctest.h"

#ifdef __cplusplus
extern "C" {
#endif

#define assert_param(expr)    ((void)0)

typedef enum
{
    RESET = 0,
    SET   = !RESET
} FlagStatus,
ITStatus;

typedef enum
{
    DISABLE = 0,
    ENABLE  = !DISABLE
} FunctionalState,
EventStatus, ControlStatus;
#define IS_FUNCTIONAL_STATE(STATE)    (((STATE) == DISABLE) || ((STATE) == ENABLE))

typedef enum
{
    ERROR   = 0,
    SUCCESS = !ERROR
} ErrorStatus;

typedef enum
{
    UNMASKED = 0,
    MASKED   = !UNMASKED
} MaskStatus;

/**
 * @brief  Driver Status structures definition
 */
typedef enum
{
    DRV_OK        = 0x00,
    DRV_ERROR     = 0x01,
    DRV_PARAM_ERR = 0x02,
    DRV_INVALID   = 0x03,
    DRV_TIMEOUT   = 0x04,
    DRV_BUSY      = 0x05
} DRV_StatusTypeDef;



/**
 * @brief AHBDMA channel register set struct typedef
 *
 */
typedef struct
{
    uint64_t SAR;                /* Channelx Source Address Register */
    uint64_t DAR;                /* Channelx Destination Address Register */
    uint64_t LLP;                /* Channelx Linked List Pointer Register */
    uint64_t CTL;                /* Channelx Control Register */
    uint64_t SSTAT;              /* Channelx Source Status Register */
    uint64_t DSTAT;              /* Channelx Destination Status Register */
    uint64_t SSTATAR;            /* Channelx Source Status Fetch Register */
    uint64_t DSTATAR;            /* Channelx Destination Status Fetch Register */
    uint64_t CFG;                /* Channelx Configuration Register */
    uint64_t SGR;                /* Channelx Source Gather Register */
    uint64_t DSR;                /* Channelx Destination Scatter Register */
} AHBDMA_Ch_TypeDef;

/**
 * @brief AHBDMA interrupt register struct typedef
 *
 */
typedef struct
{
    uint64_t RAWTFR;                /* offset:0x2c0 Raw Status for IntTfr Interrupt */
    uint64_t RAWBLOCK;              /* offset:0x2c8 Raw Status for IntBlock Interrupt */
    uint64_t RAWSRCTRAN;            /* offset:0x2d0 Raw Status for IntSrcTran Interrupt */
    uint64_t RAWDSTTRAN;            /* offset:0x2d8 Raw Status for IntDstTran Interrupt */
    uint64_t RAWERR;                /* offset:0x2e0 Raw Status for IntErr Interrupt */
    uint64_t STATUSTFR;             /* offset:0x2e8 Status for IntTfr Interrupt */
    uint64_t STATUSBLOCK;           /* offset:0x2f0 Status for IntBlock Interrupt */
    uint64_t STATUSSRCTRAN;         /* offset:0x2f8 Status for IntSrcTran Interrupt */
    uint64_t STATUSDSTTRAN;         /* offset:0x300 Status for IntDstTran Interrupt */
    uint64_t STATUSERR;             /* offset:0x308 Status for IntErr Interrupt */
    uint64_t MASKTFR;               /* offset:0x310 Status for IntTfr Interrupt */
    uint64_t MASKBLOCK;             /* offset:0x318 Mask for IntBlock Interrupt */
    uint64_t MASKSRCTRAN;           /* offset:0x320 Status for IntSrcTran Interrupt */
    uint64_t MASKDSTTRAN;           /* offset:0x328 Mask for IntDstTran Interrupt */
    uint64_t MASKERR;               /* offset:0x330 Mask for IntErr Interrupt */
    uint64_t CLEARTFR;              /* offset:0x338 Clear for IntTfr Interrupt */
    uint64_t CLEARBLOCK;            /* offset:0x340 Clear for IntBlock Interrupt */
    uint64_t CLEARSRCTRAN;          /* offset:0x348 Clear for IntSrcTran Interrupt */
    uint64_t CLEARDSTTRAN;          /* offset:0x350 Clear for IntDstTran Interrupt */
    uint64_t CLEARERR;              /* offset:0x358 Clear for IntErr Interrupt */
    uint64_t STATUSINT;             /* offset:0x360 Status for each Interrupt type */
}AHBDMA_Interrupt_TypeDef;

/**
 * @brief AHBDMA misc registers struct typedef
 *
 */
typedef struct
{
    uint64_t CFGREG;                            /* offset:0x398 AHBDMA Configuration Register */
    uint64_t CHENREG;                           /* offset:0x3a0 AHBDMA Channel Enable Register */
    uint64_t IDREG;                             /* offset:0x3a8 AHBDMA ID register */
    uint64_t TESTREG;                           /* offset:0x3b0 AHBDMA Test Register */
    uint64_t LPTIMEOUTREG;                      /* offset:0x3b8 AHBDMA Low Power Timeout Register */
    uint64_t COMP_PARAMS_6;                    /* offset:0x3c8 AHBDMA Component Parameters Register 6 */
    uint64_t COMP_PARAMS_5;                    /* offset:0x3d0 AHBDMA Component Parameters Register 5 */
    uint64_t COMP_PARAMS_4;                    /* offset:0x3d8 AHBDMA Component Parameters Register 4 */
    uint64_t COMP_PARAMS_3;                    /* offset:0x3e0 AHBDMA Component Parameters Register 3 */
    uint64_t COMP_PARAMS_2;                    /* offset:0x3e8 AHBDMA Component Parameters Register 2 */
    uint64_t COMP_PARAMS_1;                    /* offset:0x3f0 AHBDMA Component Parameters Register 1 */
    uint64_t COMPSID;                           /* offset:0x3f8 DMA Component ID register */
} AHBDMA_MISC_TypeDef;

/**
 * @brief Peripheral register for AHBDMA
 *
 */
typedef struct
{
    volatile AHBDMA_Ch_TypeDef CH[8] ;                              /*!< XXX Register,                                       Address offset: 0x0 */
    volatile AHBDMA_Interrupt_TypeDef INT;
    uint64_t reserved[6];
    volatile AHBDMA_MISC_TypeDef MISC;
} AHBDMA_TypeDef;

#define REG16(REG)                             (*(__IO uint16_t *)(REG))

#define REG32(REG)                             (*(__IO uint32_t *)(REG))

#define SET_BIT(REG, BIT)                      ((REG) |= (BIT))

#define CLEAR_BIT(REG, BIT)                    ((REG) &= ~(BIT))

#define READ_BIT(REG, BIT)                     ((REG)&(BIT))

#define CLEAR_REG(REG)                         ((REG) = (0x0))

#define WRITE_REG(REG, VAL)                    ((REG) = (VAL))

#define READ_REG(REG)                          (REG)

#define MODIFY_REG(REG, CLEARMASK, SETMASK)    WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))

#define POSITION_VAL(VAL)                      (__CLZ(__RBIT(VAL)))

#define BIT_MASK(x)                            ((uint32_t)((uint32_t)0x01U << (x)))

#define BITS_MASK(start, end)                  ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))

#define BITS_WID_MASK(width)                   (0xFFFFFFFFUL >> (32U - (uint32_t)(width)))

#define GET_BITS(regval, start, end)           (((regval)&BITS_MASK((start), (end))) >> (start))

#define OFT_REG32     (4)

#define BITS_DWORD    (32)

/********************  Bits definition for AHB DMAC Source Address Register  *******************/
#define AHBDMA_SAR_Pos (0U)
#define AHBDMA_SAR_Msk (0xFFFFFFFFUL << AHBDMA_SAR_Pos)           /*!< 0xFFFFFFFF */

/********************  Bits definition for AHB DMAC Destination Address Register  *******************/
#define AHBDMA_DAR_Pos (0U)
#define AHBDMA_DAR_Msk (0xFFFFFFFFUL << AHBDMA_DAR_Pos)           /*!< 0xFFFFFFFF */

/********************  Bits definition for AHB DMAC Linked List Pointer Register  *******************/
#define AHBDMA_LLPR_LMS_Pos (0U)
#define AHBDMA_LLPR_LMS_Msk (0x3UL << AHBDMA_LLPR_LMS_Pos)           /*!< 0xFFFFFFFF */
#define AHBDMA_LLPR_LOC_Pos (2U)
#define AHBDMA_LLPR_LOC_Msk (0xFFFFFFFCUL << AHBDMA_LLPR_LOC_Pos)           /*!< 0xFFFFFFFF */

/********************  Bits definition for AHB DMAC Control Register *******************/
#define AHBDMA_CR_INT_EN_Pos           (0U)
#define AHBDMA_CR_INT_EN_Msk           (0x1UL << AHBDMA_CR_INT_EN_Pos)
#define AHBDMA_CR_DST_TR_WIDTH_Pos     (1U)
#define AHBDMA_CR_DST_TR_WIDTH_Msk     (0x7UL << AHBDMA_CR_DST_TR_WIDTH_Pos)
#define AHBDMA_CR_SRC_TR_WIDTH_Pos     (4U)
#define AHBDMA_CR_SRC_TR_WIDTH_Msk     (0x7UL << AHBDMA_CR_SRC_TR_WIDTH_Pos)
#define AHBDMA_CR_DINC_Pos             (7U)
#define AHBDMA_CR_DINC_Msk             (0x3UL << AHBDMA_CR_DINC_Pos)
#define AHBDMA_CR_SINC_Pos             (9U)
#define AHBDMA_CR_SINC_Msk             (0x3UL << AHBDMA_CR_SINC_Pos)
#define AHBDMA_CR_DST_MSIZE_Pos        (11U)
#define AHBDMA_CR_DST_MSIZE_Msk        (0x7UL << AHBDMA_CR_DST_MSIZE_Pos)
#define AHBDMA_CR_SRC_MSIZE_Pos        (14U)
#define AHBDMA_CR_SRC_MSIZE_Msk        (0x7UL << AHBDMA_CR_SRC_MSIZE_Pos)
#define AHBDMA_CR_SRC_GATHER_EN_Pos    (17U)
#define AHBDMA_CR_SRC_GATHER_EN_Msk    (0x1UL << AHBDMA_CR_SRC_GATHER_EN_Pos)
#define AHBDMA_CR_DST_SCATTER_EN_Pos   (18U)
#define AHBDMA_CR_DST_SCATTER_EN_Msk   (0x1UL << AHBDMA_CR_DST_SCATTER_EN_Pos)
#define AHBDMA_CR_Rsvd_CTL_Pos         (19U)
#define AHBDMA_CR_Rsvd_CTL_Msk         (0x1UL << AHBDMA_CR_Rsvd_CTL_Pos)
#define AHBDMA_CR_TT_FC_Pos            (20U)
#define AHBDMA_CR_TT_FC_Msk            (0x7UL << AHBDMA_CR_TT_FC_Pos)
#define AHBDMA_CR_DMS_Pos              (23U)
#define AHBDMA_CR_DMS_Msk              (0x3UL << AHBDMA_CR_DMS_Pos)
#define AHBDMA_CR_SMS_Pos              (25U)
#define AHBDMA_CR_SMS_Msk              (0x3UL << AHBDMA_CR_SMS_Pos)
#define AHBDMA_CR_LLP_DST_EN_Pos       (27U)
#define AHBDMA_CR_LLP_DST_EN_Msk       (0x1UL << AHBDMA_CR_LLP_DST_EN_Pos)
#define AHBDMA_CR_LLP_SRC_EN_Pos       (28U)
#define AHBDMA_CR_LLP_SRC_EN_Msk       (0x1UL << AHBDMA_CR_LLP_SRC_EN_Pos)
#define AHBDMA_CR_Rsvd_1_CTL_Pos       (29U)
#define AHBDMA_CR_Rsvd_1_CTL_Msk       (0x7UL << AHBDMA_CR_Rsvd_1_CTL_Pos)
#define AHBDMA_CR_BLOCK_TS_Pos         (32U)
#define AHBDMA_CR_BLOCK_TS_Msk         (0xFFFUL << AHBDMA_CR_BLOCK_TS_Pos)
#define AHBDMA_CR_Rsvd_2_CTL_Pos       (43U)
#define AHBDMA_CR_Rsvd_2_CTL_Msk       (0x1UL << AHBDMA_CR_Rsvd_2_CTL_Pos)
#define AHBDMA_CR_DONE_Pos             (44U)
#define AHBDMA_CR_DONE_Msk             (0x1UL << AHBDMA_CR_DONE_Pos)
#define AHBDMA_CR_Rsvd_3_CTL_Pos       (45U)
#define AHBDMA_CR_Rsvd_3_CTL_Msk       (0xFFUL << AHBDMA_CR_Rsvd_3_CTL_Pos)

/********************  Bits definition for AHB DMAC Configuration Register  *******************/
#define AHBDMA_CFG_Rsvd_Pos                        (0U)
#define AHBDMA_CFG_Rsvd_Msk                        (0x1FUL << AHBDMA_CFG_Rsvd_Pos)
#define AHBDMA_CFG_CH_PRIOR_Pos                    (5U)
#define AHBDMA_CFG_CH_PRIOR_Msk                    (0x7UL << AHBDMA_CFG_CH_PRIOR_Pos)
#define AHBDMA_CFG_CH_SUSP_Pos                     (8U)
#define AHBDMA_CFG_CH_SUSP_Msk                     (0x1UL << AHBDMA_CFG_CH_SUSP_Pos)
#define AHBDMA_CFG_FIFO_EMPTY_Pos                  (9U)
#define AHBDMA_CFG_FIFO_EMPTY_Msk                  (0x1UL << AHBDMA_CFG_FIFO_EMPTY_Pos)
#define AHBDMA_CFG_HS_SEL_DST_Pos                  (10U)
#define AHBDMA_CFG_HS_SEL_DST_Msk                  (0x1UL << AHBDMA_CFG_HS_SEL_DST_Pos)
#define AHBDMA_CFG_HS_SEL_SRC_Pos                  (11U)
#define AHBDMA_CFG_HS_SEL_SRC_Msk                  (0x1UL << AHBDMA_CFG_HS_SEL_SRC_Pos)
#define AHBDMA_CFG_LOCK_CH_L_Pos                   (12U)
#define AHBDMA_CFG_LOCK_CH_L_Msk                   (0x3UL << AHBDMA_CFG_LOCK_CH_L_Pos)
#define AHBDMA_CFG_LOCK_B_L_Pos                    (14U)
#define AHBDMA_CFG_LOCK_B_L_Msk                    (0x3UL << AHBDMA_CFG_LOCK_B_L_Pos)
#define AHBDMA_CFG_LOCK_CH_Pos                     (16U)
#define AHBDMA_CFG_LOCK_CH_Msk                     (0x1UL << AHBDMA_CFG_LOCK_CH_Pos)
#define AHBDMA_CFG_LOCK_B_Pos                      (17U)
#define AHBDMA_CFG_LOCK_B_Msk                      (0x1UL << AHBDMA_CFG_LOCK_B_Pos)
#define AHBDMA_CFG_DST_HS_POL_Pos                  (18U)
#define AHBDMA_CFG_DST_HS_POL_Msk                  (0x1UL << AHBDMA_CFG_DST_HS_POL_Pos)
#define AHBDMA_CFG_SRC_HS_POL_Pos                  (19U)
#define AHBDMA_CFG_SRC_HS_POL_Msk                  (0x1UL << AHBDMA_CFG_SRC_HS_POL_Pos)
#define AHBDMA_CFG_MAX_ABRST_Pos                   (20U)
#define AHBDMA_CFG_MAX_ABRST_Msk                   (0x1UL << AHBDMA_CFG_MAX_ABRST_Pos)
#define AHBDMA_CFG_RELOAD_SRC_Pos                  (30U)
#define AHBDMA_CFG_RELOAD_SRC_Msk                  (0x3FFUL << AHBDMA_CFG_RELOAD_SRC_Pos)
#define AHBDMA_CFG_RELOAD_DST_Pos                  (31U)
#define AHBDMA_CFG_RELOAD_DST_Msk                  (0x1UL << AHBDMA_CFG_RELOAD_DST_Pos)
#define AHBDMA_CFG_FCMODE_Pos                      (32U)
#define AHBDMA_CFG_FCMODE_Msk                      (0x1UL << AHBDMA_CFG_FCMODE_Pos)
#define AHBDMA_CFG_FIFO_MODE_Pos                   (33U)
#define AHBDMA_CFG_FIFO_MODE_Msk                   (0x1UL << AHBDMA_CFG_FIFO_MODE_Pos)
#define AHBDMA_CFG_PROTCTL_Pos                     (34U)
#define AHBDMA_CFG_PROTCTL_Msk                     (0x7UL << AHBDMA_CFG_PROTCTL_Pos)
#define AHBDMA_CFG_DS_UPD_EN_Pos                   (37U)
#define AHBDMA_CFG_DS_UPD_EN_Msk                   (0x1UL << AHBDMA_CFG_DS_UPD_EN_Pos)
#define AHBDMA_CFG_SS_UPD_EN_Pos                   (38U)
#define AHBDMA_CFG_SS_UPD_EN_Msk                   (0x1UL << AHBDMA_CFG_SS_UPD_EN_Pos)
#define AHBDMA_CFG_SRC_PER_Pos                     (39U)
#define AHBDMA_CFG_SRC_PER_Msk                     (0x7UL << AHBDMA_CFG_SRC_PER_Pos)
#define AHBDMA_CFG_Rsvd_1_Pos                      (42U)
#define AHBDMA_CFG_Rsvd_1_Msk                      (0x1UL << AHBDMA_CFG_Rsvd_1_Pos)
#define AHBDMA_CFG_DST_PER_Pos                    (43U)
#define AHBDMA_CFG_DST_PER_Msk                    (0x7UL << AHBDMA_CFG_DST_PER_Pos)
#define AHBDMA_CFG_Rsvd_2_Pos                      (46U)
#define AHBDMA_CFG_Rsvd_2_Msk                      (0x1UL << AHBDMA_CFG_Rsvd_2_Pos)
#define AHBDMA_CFG_Rsvd_3_Pos                      (47U)
#define AHBDMA_CFG_Rsvd_3_Msk                      (0x1FFUL << AHBDMA_CFG_Rsvd_3_Pos)

/********************  Bits definition for AHB DMAC Source Gather Register  *******************/
#define AHBDMA_SGR_SGI_Pos                      (0U)
#define AHBDMA_SGR_SGI_Msk                      (0xFFFFFUL << AHBDMA_SGR_SGI_Pos)
#define AHBDMA_SGR_SGC_Pos                      (20U)
#define AHBDMA_SGR_SGC_Msk                      (0xFFFUL << AHBDMA_SGR_SGC_Pos)

/********************  Bits definition for AHB DMAC Destination Scatter Register  *******************/
#define AHBDMA_DSR_SGI_Pos                      (0U)
#define AHBDMA_DSR_SGI_Msk                      (0xFFFFFUL << AHBDMA_DSR_SGI_Pos)
#define AHBDMA_DSR_SGC_Pos                      (20U)
#define AHBDMA_DSR_SGC_Msk                      (0xFFFUL << AHBDMA_DSR_SGC_Pos)

/********************  Bits definition for AHB DMAC Interrupt Register *******************/
/********************  Bits definition for AHB DMAC Raw Status Register *******************/
#define AHBDMA_INTR_RAW_Pos                      (0U)
#define AHBDMA_INTR_RAW_Msk                      (0xFFUL << AHBDMA_INTR_RAW_Pos)

/********************  Bits definition for AHB DMAC Raw Status for IntBlock Interrupt Register *******************/
#define AHBDMA_INTR_RawBlock_Pos                      (0U)
#define AHBDMA_INTR_RawBlock_Msk                      (0xFFUL << AHBDMA_INTR_RawBlock_Pos)

/********************  Bits definition for AHB DMAC Raw Status for IntSrcTran Interrupt Register *******************/
#define AHBDMA_INTR_RawSrcTran_Pos                      (0U)
#define AHBDMA_INTR_RawSrcTran_Msk                      (0xFFUL << AHBDMA_INTR_RawSrcTran_Pos)

/********************  Bits definition for AHB DMAC Raw Status for IntDstTran Interrupt Register *******************/
#define AHBDMA_INTR_RawDstTran_Pos                      (0U)
#define AHBDMA_INTR_RawDstTran_Msk                      (0xFFUL << AHBDMA_INTR_RawDstTran_Pos)

/********************  Bits definition for AHB DMAC Raw Status for IntErr Interrupt Register *******************/
#define AHBDMA_INTR_RawErr_Pos                      (0U)
#define AHBDMA_INTR_RawErr_Msk                      (0xFFUL << AHBDMA_INTR_RawErr_Pos)

/********************  Bits definition for AHB DMAC Status for IntTfr Interrupt Register *******************/
#define AHBDMA_INTR_StatusTfr_Pos                      (0U)
#define AHBDMA_INTR_StatusTfr_Msk                      (0xFFUL << AHBDMA_INTR_StatusTfr_Pos)

/********************  Bits definition for AHB DMAC Status for IntBlock Interrupt Register *******************/
#define AHBDMA_INTR_StatusBlock_Pos                      (0U)
#define AHBDMA_INTR_StatusBlock_Msk                      (0xFFUL << AHBDMA_INTR_StatusBlock_Pos)

/********************  Bits definition for AHB DMAC Status for IntSrcTran Interrupt Register *******************/
#define AHBDMA_INTR_StatusSrcTran_Pos                      (0U)
#define AHBDMA_INTR_StatusSrcTran_Msk                      (0xFFUL << AHBDMA_INTR_StatusSrcTran_Pos)

/********************  Bits definition for AHB DMAC Status for IntDstTran Interrupt Register *******************/
#define AHBDMA_INTR_StatusDstTran_Pos                      (0U)
#define AHBDMA_INTR_StatusDstTran_Msk                      (0xFFUL << AHBDMA_INTR_StatusDstTran_Pos)

/********************  Bits definition for AHB DMAC Status for IntErr Interrupt Register *******************/
#define AHBDMA_INTR_StatusErr_Pos                      (0U)
#define AHBDMA_INTR_StatusErr_Msk                      (0xFFUL << AHBDMA_INTR_StatusErr_Pos)

/********************  Bits definition for AHB DMAC Status for IntTfr Interrupt Register *******************/
#define AHBDMA_INTR_MaskTfr_Pos                      (0U)
#define AHBDMA_INTR_MaskTfr_Msk                      (0xFFUL << AHBDMA_INTR_MaskTfr_Pos)

/********************  Bits definition for AHB DMAC Mask for IntBlock Interrupt Register *******************/
#define AHBDMA_INTR_Block_INT_MASK_Pos                      (0U)
#define AHBDMA_INTR_Block_INT_MASK_Msk                      (0xFFUL << AHBDMA_INTR_INT_Block_MASK_Pos)
#define AHBDMA_INTR_Block_INT_MASK_WE_Pos                      (8U)
#define AHBDMA_INTR_Block_INT_MASK_WE_Msk                      (0xFFUL << AHBDMA_INTR_INT_Block_MASK_Pos)

/********************  Bits definition for AHB DMAC Status for IntSrcTran Interrupt Register *******************/
#define AHBDMA_INTR_Src_INT_MASK_Pos                         (0U)
#define AHBDMA_INTR_Src_INT_MASK_Msk                         (0xFFUL << AHBDMA_INTR_Src_INT_MASK_Pos)
#define AHBDMA_INTR_Src_INT_MASK_WE_Pos                      (8U)
#define AHBDMA_INTR_Src_INT_MASK_WE_Msk                      (0xFFUL << AHBDMA_INTR_Src_INT_MASK_Pos)

/********************  Bits definition for AHB DMAC Status for IntDstTran Interrupt Register *******************/
#define AHBDMA_INTR_Dsc_INT_MASK_Pos                         (0U)
#define AHBDMA_INTR_Dsc_INT_MASK_Msk                         (0xFFUL << AHBDMA_INTR_Dsc_INT_MASK_Pos)
#define AHBDMA_INTR_Dsc_INT_MASK_WE_Pos                      (8U)
#define AHBDMA_INTR_Dsc_INT_MASK_WE_Msk                      (0xFFUL << AHBDMA_INTR_Dsc_INT_MASK_Pos)

/********************  Bits definition for AHB DMAC Status for IntErr Interrupt Register *******************/
#define AHBDMA_INTR_Err_INT_MASK_Pos                         (0U)
#define AHBDMA_INTR_Err_INT_MASK_Msk                         (0xFFUL << AHBDMA_INTR_Err_INT_MASK_Pos)
#define AHBDMA_INTR_Err_INT_MASK_WE_Pos                      (8U)
#define AHBDMA_INTR_Err_INT_MASK_WE_Msk                      (0xFFUL << AHBDMA_INTR_Err_INT_MASK_Pos)

/********************  Bits definition for AHB DMAC Clear for IntTfr Interrupt Register *******************/
#define AHBDMA_INTR_CLEAR_IntTfr_Pos                         (0U)
#define AHBDMA_INTR_CLEAR_IntTfr_Msk                         (0xFFUL << AHBDMA_INTR_CLEAR_IntTfr_Pos)

/********************  Bits definition for AHB DMAC Clear for IntBlock Interrupt Register *******************/
#define AHBDMA_INTR_CLEAR_IntBlock_Pos                         (0U)
#define AHBDMA_INTR_CLEAR_IntBlock_Msk                         (0xFFUL << AHBDMA_INTR_CLEAR_IntBlock_Pos)

/********************  Bits definition for AHB DMAC Clear for IntSrcTran Interrupt Register *******************/
#define AHBDMA_INTR_CLEAR_IntSrcTran_Pos                         (0U)
#define AHBDMA_INTR_CLEAR_IntSrcTran_Msk                         (0xFFUL << AHBDMA_INTR_CLEAR_IntSrcTran_Pos)

/********************  Bits definition for AHB DMAC Clear for IntDstTran Interrupt Register *******************/
#define AHBDMA_INTR_CLEAR_IntDstTran_Pos                         (0U)
#define AHBDMA_INTR_CLEAR_IntDstTran_Msk                         (0xFFUL << AHBDMA_INTR_CLEAR_IntDstTran_Pos)

/********************  Bits definition for AHB DMAC Clear for IntErr Interrupt Register *******************/
#define AHBDMA_INTR_CLEAR_IntErr_Pos                         (0U)
#define AHBDMA_INTR_CLEAR_IntErr_Msk                         (0xFFUL << AHBDMA_INTR_CLEAR_IntErr_Pos)

/********************  Bits definition for AHB DMAC Status for each Interrupt type Register *******************/
#define AHBDMA_INTR_STATUS_TFR_Pos                         (0U)
#define AHBDMA_INTR_STATUS_TFR_Msk                         (0x1UL << AHBDMA_INTR_STATUS_TFR_Pos)
#define AHBDMA_INTR_STATUS_BLOCK_Pos                       (1U)
#define AHBDMA_INTR_STATUS_BLOCK_Msk                       (0x1UL << AHBDMA_INTR_STATUS_BLOCK_Pos)
#define AHBDMA_INTR_STATUS_SRCT_Pos                        (2U)
#define AHBDMA_INTR_STATUS_SRCT_Msk                        (0x1UL << AHBDMA_INTR_STATUS_SRCT_Pos)
#define AHBDMA_INTR_STATUS_DSTT_Pos                        (3U)
#define AHBDMA_INTR_STATUS_DSTT_Msk                        (0x1UL << AHBDMA_INTR_STATUS_DSTT_Pos)
#define AHBDMA_INTR_STATUS_ERR_Pos                         (4U)
#define AHBDMA_INTR_STATUS_ERR_Msk                         (0x1UL << AHBDMA_INTR_STATUS_ERR_Pos)

/********************  Bits definition for AHB DMAC Software_Handshake Register *******************/
/********************  Bits definition for AHB DMAC Source Software Transaction Request Register *******************/
#define AHBDMA_SOFT_HS_SRC_REQ_Pos                            (0U)
#define AHBDMA_SOFT_HS_SRC_REQ_Msk                            (0xFFUL << AHBDMA_SOFT_HS_SRC_REQ_Pos)
#define AHBDMA_SOFT_HS_SRC_REQ_WE_Pos                         (8U)
#define AHBDMA_SOFT_HS_SRC_REQ_WE_Msk                         (0xFFUL << AHBDMA_SOFT_HS_SRC_REQ_WE_Pos)

/********************  Bits definition for AHB DMAC Destination Software Transaction Request Register *******************/
#define AHBDMA_SOFT_HS_DST_REQ_Pos                            (0U)
#define AHBDMA_SOFT_HS_DST_REQ_Msk                            (0xFFUL << AHBDMA_SOFT_HS_DST_REQ_Pos)
#define AHBDMA_SOFT_HS_DST_REQ_WE_Pos                         (8U)
#define AHBDMA_SOFT_HS_DST_REQ_WE_Msk                         (0xFFUL << AHBDMA_SOFT_HS_DST_REQ_WE_Pos)

/********************  Bits definition for AHB DMAC Source Single Transaction Request Register *******************/
#define AHBDMA_SOFT_HS_SRC_SGLREQ_Pos                            (0U)
#define AHBDMA_SOFT_HS_SRC_SGLREQ_Msk                            (0xFFUL << AHBDMA_SOFT_HS_SGLREQ_REQ_Pos)
#define AHBDMA_SOFT_HS_SRC_SGLREQ_WE_Pos                         (8U)
#define AHBDMA_SOFT_HS_SRC_SGLREQ_WE_Msk                         (0xFFUL << AHBDMA_SOFT_HS_SGLREQ_REQ_WE_Pos)

/********************  Bits definition for AHB DMAC Destination Software Transaction Request Register *******************/
#define AHBDMA_SOFT_HS_DST_SGLREQ_Pos                            (0U)
#define AHBDMA_SOFT_HS_DST_SGLREQ_Msk                            (0xFFUL << AHBDMA_SOFT_HS_DST_SGLREQ_Pos)
#define AHBDMA_SOFT_HS_DST_SGLREQ_WE_Pos                         (8U)
#define AHBDMA_SOFT_HS_DST_SGLREQ_WE_Msk                         (0xFFUL << AHBDMA_SOFT_HS_DST_SGLREQ_WE_Pos)

/********************  Bits definition for AHB DMAC Source Last Transaction Request Register *******************/
#define AHBDMA_SOFT_HS_LSTSRC_Pos                            (0U)
#define AHBDMA_SOFT_HS_LSTSRC_Msk                            (0xFFUL << AHBDMA_SOFT_HS_LSTSRC_Pos)
#define AHBDMA_SOFT_HS_LSTSRC_WE_Pos                         (8U)
#define AHBDMA_SOFT_HS_LSTSRC_WE_Msk                         (0xFFUL << AHBDMA_SOFT_HS_LSTSRC_WE_Pos)

/********************  Bits definition for AHB DMAC Destination Last Transaction Request Register *******************/
#define AHBDMA_SOFT_HS_LSTDST_Pos                            (0U)
#define AHBDMA_SOFT_HS_LSTDST_Msk                            (0xFFUL << AHBDMA_SOFT_HS_LSTDST_Pos)
#define AHBDMA_SOFT_HS_LSTDST_WE_Pos                         (8U)
#define AHBDMA_SOFT_HS_LSTDST_WE_Msk                         (0xFFUL << AHBDMA_SOFT_HS_LSTDST_WE_Pos)

/********************  Bits definition for AHB DMAC Miscellaneous Register *******************/
#define AHBDMA_MISC_CFG_Pos                            (0U)
#define AHBDMA_MISC_CFG_Msk                            (0x1UL << AHBDMA_MISC_CFG_Pos)

/********************  Bits definition for AHB DMAC Channel Enable Register *******************/
#define AHBDMA_MISC_CHx_EN_Pos                                (0U)
#define AHBDMA_MISC_CHx_EN_Msk                                (0xFFUL << AHBDMA_MISC_CHx_EN_Pos)
#define AHBDMA_MISC_CHx_EN_WE_Pos                             (0U)
#define AHBDMA_MISC_CHx_EN_WE_Msk                             (0xFFUL << AHBDMA_MISC_CHx_EN_WE_Pos)

/********************  Bits definition for AHB DMAC ID Register *******************/
#define AHBDMA_MISC_ID_Pos                            (0U)
#define AHBDMA_MISC_ID_Msk                            (0xFFFFFFFFUL << AHBDMA_MISC_ID_Pos)

/********************  Bits definition for AHB DMAC Test Register *******************/
#define AHBDMA_MISC_TEST_SLV_IF_Pos                            (0U)
#define AHBDMA_MISC_TEST_SLV_IF_Msk                            (0x1UL << AHBDMA_MISC_TEST_SLV_IF_Pos)

/********************  Bits definition for AHB DMAC Low Power Timeout Register *******************/
#define AHBDMA_MISC_LP_TIMEOUT_Pos                            (0U)
#define AHBDMA_MISC_LP_TIMEOUT_Msk                            (0x1UL << AHBDMA_MISC_LP_TIMEOUT_Pos)

/********************  Bits definition for AHB DMAC Component Parameters Register 6 *******************/
#define AHBDMA_MISC_Rsvd_DMA_COMP_PARAMS_6_Pos                 (0)
#define AHBDMA_MISC_Rsvd_DMA_COMP_PARAMS_6_Msk                 (0xFFFFFFFFUL << AHBDMA_MISC_Rsvd_DMA_COMP_PARAMS_6_Pos)
#define AHBDMA_MISC_CH7_DTW_Pos                                (32U)
#define AHBDMA_MISC_CH7_DTW_Msk                                (0x7UL << AHBDMA_MISC_CH7_DTW_Pos)
#define AHBDMA_MISC_CH7_STW_Pos                                (35U)
#define AHBDMA_MISC_CH7_STW_Msk                                (0x7UL << AHBDMA_MISC_CH7_STW_Pos)
#define AHBDMA_MISC_CH7_STAT_DST_Pos                           (38U)
#define AHBDMA_MISC_CH7_STAT_DST_Msk                           (0x1UL << AHBDMA_MISC_CH7_STAT_DST_Pos)
#define AHBDMA_MISC_CH7_STAT_SRC_Pos                           (39U)
#define AHBDMA_MISC_CH7_STAT_SRC_Msk                           (0x1UL << AHBDMA_MISC_CH7_STAT_SRC_Pos)
#define AHBDMA_MISC_CH7_DST_SCA_EN_Pos                         (40U)
#define AHBDMA_MISC_CH7_DST_SCA_EN_Msk                         (0x1UL << AHBDMA_MISC_CH7_DST_SCA_EN_Pos)
#define AHBDMA_MISC_CH7_SRC_GAT_EN_Pos                         (41U)
#define AHBDMA_MISC_CH7_SRC_GAT_EN_Msk                         (0x1UL << AHBDMA_MISC_CH7_SRC_GAT_EN_Pos)
#define AHBDMA_MISC_CH7_LOCK_EN_Pos                            (42U)
#define AHBDMA_MISC_CH7_LOCK_EN_Msk                            (0x1UL << AHBDMA_MISC_CH7_LOCK_EN_Pos)
#define AHBDMA_MISC_CH7_MULTI_BLK_EN_Pos                       (43U)
#define AHBDMA_MISC_CH7_MULTI_BLK_EN_Msk                       (0x1UL << AHBDMA_MISC_CH7_MULTI_BLK_EN_Pos)
#define AHBDMA_MISC_CH7_CTL_WB_EN_Pos                          (44U)
#define AHBDMA_MISC_CH7_CTL_WB_EN_Msk                          (0x1UL << AHBDMA_MISC_CH7_CTL_WB_EN_Pos)
#define AHBDMA_MISC_CH7_HC_LLP_Pos                             (45U)
#define AHBDMA_MISC_CH7_HC_LLP_Msk                             (0x1UL << AHBDMA_MISC_CH7_HC_LLP_Pos)
#define AHBDMA_MISC_CH7_FC_Pos                                 (46U)
#define AHBDMA_MISC_CH7_FC_Msk                                 (0x3UL << AHBDMA_MISC_CH7_FC_Pos)
#define AHBDMA_MISC_CH7_MAX_MULT_SIZE_Pos                      (48U)
#define AHBDMA_MISC_CH7_MAX_MULT_SIZE_Msk                      (0x7UL << AHBDMA_MISC_CH7_MAX_MULT_SIZE_Pos)
#define AHBDMA_MISC_CH7_DMS_Pos                                (51U)
#define AHBDMA_MISC_CH7_DMS_Msk                                (0x7UL << AHBDMA_MISC_CH7_DMS_Pos)
#define AHBDMA_MISC_CH7_LMS_Pos                                (54U)
#define AHBDMA_MISC_CH7_LMS_Msk                                (0x7UL << AHBDMA_MISC_CH7_LMS_Pos)
#define AHBDMA_MISC_CH7_SMS_Pos                                (57U)
#define AHBDMA_MISC_CH7_SMS_Msk                                (0x7UL << AHBDMA_MISC_CH7_SMS_Pos)
#define AHBDMA_MISC_CH7_FIFO_DEPTH_Pos                         (60U)
#define AHBDMA_MISC_CH7_FIFO_DEPTH_Msk                         (0x7UL << AHBDMA_MISC_CH7_FIFO_DEPTH_Pos)
#define AHBDMA_MISC_Rsvd_1_DMA_COMP_PARAMS_6_Pos               (63U)
#define AHBDMA_MISC_Rsvd_1_DMA_COMP_PARAMS_6_Msk               (0x1UL << AHBDMA_MISC_Rsvd_1_DMA_COMP_PARAMS_6_Pos)

/********************  Bits definition for AHB DMAC Component Parameters Register 5 *******************/
#define AHBDMA_MISC_CH6_DTW_Pos                                (0U)
#define AHBDMA_MISC_CH6_DTW_Msk                                (0x7UL << AHBDMA_MISC_CH6_DTW_Pos)
#define AHBDMA_MISC_CH6_STW_Pos                                (3U)
#define AHBDMA_MISC_CH6_STW_Msk                                (0x7UL << AHBDMA_MISC_CH6_STW_Pos)
#define AHBDMA_MISC_CH6_STAT_DST_Pos                           (6U)
#define AHBDMA_MISC_CH6_STAT_DST_Msk                           (0x1UL << AHBDMA_MISC_CH6_STAT_DST_Pos)
#define AHBDMA_MISC_CH6_STAT_SRC_Pos                           (7U)
#define AHBDMA_MISC_CH6_STAT_SRC_Msk                           (0x1UL << AHBDMA_MISC_CH6_STAT_SRC_Pos)
#define AHBDMA_MISC_CH6_DST_SCA_EN_Pos                         (8U)
#define AHBDMA_MISC_CH6_DST_SCA_EN_Msk                         (0x1UL << AHBDMA_MISC_CH6_DST_SCA_EN_Pos)
#define AHBDMA_MISC_CH6_SRC_GAT_EN_Pos                         (9U)
#define AHBDMA_MISC_CH6_SRC_GAT_EN_Msk                         (0x1UL << AHBDMA_MISC_CH6_SRC_GAT_EN_Pos)
#define AHBDMA_MISC_CH6_LOCK_EN_Pos                            (10U)
#define AHBDMA_MISC_CH6_LOCK_EN_Msk                            (0x1UL << AHBDMA_MISC_CH6_LOCK_EN_Pos)
#define AHBDMA_MISC_CH6_MULTI_BLK_EN_Pos                       (11U)
#define AHBDMA_MISC_CH6_MULTI_BLK_EN_Msk                       (0x1UL << AHBDMA_MISC_CH6_MULTI_BLK_EN_Pos)
#define AHBDMA_MISC_CH6_CTL_WB_EN_Pos                          (12U)
#define AHBDMA_MISC_CH6_CTL_WB_EN_Msk                          (0x1UL << AHBDMA_MISC_CH6_CTL_WB_EN_Pos)
#define AHBDMA_MISC_CH6_HC_LLP_Pos                             (13U)
#define AHBDMA_MISC_CH6_HC_LLP_Msk                             (0x1UL << AHBDMA_MISC_CH6_HC_LLP_Pos)
#define AHBDMA_MISC_CH6_FC_Pos                                 (14U)
#define AHBDMA_MISC_CH6_FC_Msk                                 (0x3UL << AHBDMA_MISC_CH6_FC_Pos)
#define AHBDMA_MISC_CH6_MAX_MULT_SIZE_Pos                      (16U)
#define AHBDMA_MISC_CH6_MAX_MULT_SIZE_Msk                      (0x7UL << AHBDMA_MISC_CH6_MAX_MULT_SIZE_Pos)
#define AHBDMA_MISC_CH6_DMS_Pos                                (19U)
#define AHBDMA_MISC_CH6_DMS_Msk                                (0x7UL << AHBDMA_MISC_CH6_DMS_Pos)
#define AHBDMA_MISC_CH6_LMS_Pos                                (22U)
#define AHBDMA_MISC_CH6_LMS_Msk                                (0x7UL << AHBDMA_MISC_CH6_LMS_Pos)
#define AHBDMA_MISC_CH6_SMS_Pos                                (25U)
#define AHBDMA_MISC_CH6_SMS_Msk                                (0x7UL << AHBDMA_MISC_CH6_SMS_Pos)
#define AHBDMA_MISC_CH6_FIFO_DEPTH_Pos                         (28U)
#define AHBDMA_MISC_CH6_FIFO_DEPTH_Msk                         (0x7UL << AHBDMA_MISC_CH6_FIFO_DEPTH_Pos)
#define AHBDMA_MISC_Rsvd_DMA_COMP_PARAMS_5_Pos                 (31U)
#define AHBDMA_MISC_Rsvd_DMA_COMP_PARAMS_5_Msk                 (0x1UL << AHBDMA_MISC_Rsvd_DMA_COMP_PARAMS_5_Pos)
#define AHBDMA_MISC_CH5_DTW_Pos                                (32U)
#define AHBDMA_MISC_CH5_DTW_Msk                                (0x7UL << AHBDMA_MISC_CH5_DTW_Pos)
#define AHBDMA_MISC_CH5_STW_Pos                                (35U)
#define AHBDMA_MISC_CH5_STW_Msk                                (0x7UL << AHBDMA_MISC_CH5_STW_Pos)
#define AHBDMA_MISC_CH5_STAT_DST_Pos                           (38U)
#define AHBDMA_MISC_CH5_STAT_DST_Msk                           (0x1UL << AHBDMA_MISC_CH5_STAT_DST_Pos)
#define AHBDMA_MISC_CH5_STAT_SRC_Pos                           (39U)
#define AHBDMA_MISC_CH5_STAT_SRC_Msk                           (0x1UL << AHBDMA_MISC_CH5_STAT_SRC_Pos)
#define AHBDMA_MISC_CH5_DST_SCA_EN_Pos                         (40U)
#define AHBDMA_MISC_CH5_DST_SCA_EN_Msk                         (0x1UL << AHBDMA_MISC_CH5_DST_SCA_EN_Pos)
#define AHBDMA_MISC_CH5_SRC_GAT_EN_Pos                         (41U)
#define AHBDMA_MISC_CH5_SRC_GAT_EN_Msk                         (0x1UL << AHBDMA_MISC_CH5_SRC_GAT_EN_Pos)
#define AHBDMA_MISC_CH5_LOCK_EN_Pos                            (42U)
#define AHBDMA_MISC_CH5_LOCK_EN_Msk                            (0x1UL << AHBDMA_MISC_CH5_LOCK_EN_Pos)
#define AHBDMA_MISC_CH5_MULTI_BLK_EN_Pos                       (43U)
#define AHBDMA_MISC_CH5_MULTI_BLK_EN_Msk                       (0x1UL << AHBDMA_MISC_CH5_MULTI_BLK_EN_Pos)
#define AHBDMA_MISC_CH5_CTL_WB_EN_Pos                          (44U)
#define AHBDMA_MISC_CH5_CTL_WB_EN_Msk                          (0x1UL << AHBDMA_MISC_CH5_CTL_WB_EN_Pos)
#define AHBDMA_MISC_CH5_HC_LLP_Pos                             (45U)
#define AHBDMA_MISC_CH5_HC_LLP_Msk                             (0x1UL << AHBDMA_MISC_CH5_HC_LLP_Pos)
#define AHBDMA_MISC_CH5_FC_Pos                                 (46U)
#define AHBDMA_MISC_CH5_FC_Msk                                 (0x3UL << AHBDMA_MISC_CH5_FC_Pos)
#define AHBDMA_MISC_CH5_MAX_MULT_SIZE_Pos                      (48U)
#define AHBDMA_MISC_CH5_MAX_MULT_SIZE_Msk                      (0x7UL << AHBDMA_MISC_CH5_MAX_MULT_SIZE_Pos)
#define AHBDMA_MISC_CH5_DMS_Pos                                (51U)
#define AHBDMA_MISC_CH5_DMS_Msk                                (0x7UL << AHBDMA_MISC_CH5_DMS_Pos)
#define AHBDMA_MISC_CH5_LMS_Pos                                (54U)
#define AHBDMA_MISC_CH5_LMS_Msk                                (0x7UL << AHBDMA_MISC_CH5_LMS_Pos)
#define AHBDMA_MISC_CH5_SMS_Pos                                (57U)
#define AHBDMA_MISC_CH5_SMS_Msk                                (0x7UL << AHBDMA_MISC_CH5_SMS_Pos)
#define AHBDMA_MISC_CH5_FIFO_DEPTH_Pos                         (60U)
#define AHBDMA_MISC_CH5_FIFO_DEPTH_Msk                         (0x7UL << AHBDMA_MISC_CH5_FIFO_DEPTH_Pos)
#define AHBDMA_MISC_Rsvd_1_DMA_COMP_PARAMS_5_Pos               (63U)
#define AHBDMA_MISC_Rsvd_1_DMA_COMP_PARAMS_5_Msk               (0x1UL << AHBDMA_MISC_Rsvd_1_DMA_COMP_PARAMS_5_Pos)

/********************  Bits definition for AHB DMAC Component Parameters Register 4 *******************/
#define AHBDMA_MISC_CH4_DTW_Pos                                (0U)
#define AHBDMA_MISC_CH4_DTW_Msk                                (0x7UL << AHBDMA_MISC_CH4_DTW_Pos)
#define AHBDMA_MISC_CH4_STW_Pos                                (3U)
#define AHBDMA_MISC_CH4_STW_Msk                                (0x7UL << AHBDMA_MISC_CH4_STW_Pos)
#define AHBDMA_MISC_CH4_STAT_DST_Pos                           (6U)
#define AHBDMA_MISC_CH4_STAT_DST_Msk                           (0x1UL << AHBDMA_MISC_CH4_STAT_DST_Pos)
#define AHBDMA_MISC_CH4_STAT_SRC_Pos                           (7U)
#define AHBDMA_MISC_CH4_STAT_SRC_Msk                           (0x1UL << AHBDMA_MISC_CH4_STAT_SRC_Pos)
#define AHBDMA_MISC_CH4_DST_SCA_EN_Pos                         (8U)
#define AHBDMA_MISC_CH4_DST_SCA_EN_Msk                         (0x1UL << AHBDMA_MISC_CH4_DST_SCA_EN_Pos)
#define AHBDMA_MISC_CH4_SRC_GAT_EN_Pos                         (9U)
#define AHBDMA_MISC_CH4_SRC_GAT_EN_Msk                         (0x1UL << AHBDMA_MISC_CH4_SRC_GAT_EN_Pos)
#define AHBDMA_MISC_CH4_LOCK_EN_Pos                            (10U)
#define AHBDMA_MISC_CH4_LOCK_EN_Msk                            (0x1UL << AHBDMA_MISC_CH4_LOCK_EN_Pos)
#define AHBDMA_MISC_CH4_MULTI_BLK_EN_Pos                       (11U)
#define AHBDMA_MISC_CH4_MULTI_BLK_EN_Msk                       (0x1UL << AHBDMA_MISC_CH4_MULTI_BLK_EN_Pos)
#define AHBDMA_MISC_CH4_CTL_WB_EN_Pos                          (12U)
#define AHBDMA_MISC_CH4_CTL_WB_EN_Msk                          (0x1UL << AHBDMA_MISC_CH4_CTL_WB_EN_Pos)
#define AHBDMA_MISC_CH4_HC_LLP_Pos                             (13U)
#define AHBDMA_MISC_CH4_HC_LLP_Msk                             (0x1UL << AHBDMA_MISC_CH4_HC_LLP_Pos)
#define AHBDMA_MISC_CH4_FC_Pos                                 (14U)
#define AHBDMA_MISC_CH4_FC_Msk                                 (0x3UL << AHBDMA_MISC_CH4_FC_Pos)
#define AHBDMA_MISC_CH4_MAX_MULT_SIZE_Pos                      (16U)
#define AHBDMA_MISC_CH4_MAX_MULT_SIZE_Msk                      (0x7UL << AHBDMA_MISC_CH4_MAX_MULT_SIZE_Pos)
#define AHBDMA_MISC_CH4_DMS_Pos                                (19U)
#define AHBDMA_MISC_CH4_DMS_Msk                                (0x7UL << AHBDMA_MISC_CH4_DMS_Pos)
#define AHBDMA_MISC_CH4_LMS_Pos                                (22U)
#define AHBDMA_MISC_CH4_LMS_Msk                                (0x7UL << AHBDMA_MISC_CH4_LMS_Pos)
#define AHBDMA_MISC_CH4_SMS_Pos                                (25U)
#define AHBDMA_MISC_CH4_SMS_Msk                                (0x7UL << AHBDMA_MISC_CH4_SMS_Pos)
#define AHBDMA_MISC_CH4_FIFO_DEPTH_Pos                         (28U)
#define AHBDMA_MISC_CH4_FIFO_DEPTH_Msk                         (0x7UL << AHBDMA_MISC_CH4_FIFO_DEPTH_Pos)
#define AHBDMA_MISC_Rsvd_DMA_COMP_PARAMS_4_Pos                 (31U)
#define AHBDMA_MISC_Rsvd_DMA_COMP_PARAMS_4_Msk                 (0x1UL << AHBDMA_MISC_Rsvd_DMA_COMP_PARAMS_4_Pos)
#define AHBDMA_MISC_CH3_DTW_Pos                                (32U)
#define AHBDMA_MISC_CH3_DTW_Msk                                (0x7UL << AHBDMA_MISC_CH3_DTW_Pos)
#define AHBDMA_MISC_CH3_STW_Pos                                (35U)
#define AHBDMA_MISC_CH3_STW_Msk                                (0x7UL << AHBDMA_MISC_CH3_STW_Pos)
#define AHBDMA_MISC_CH3_STAT_DST_Pos                           (38U)
#define AHBDMA_MISC_CH3_STAT_DST_Msk                           (0x1UL << AHBDMA_MISC_CH3_STAT_DST_Pos)
#define AHBDMA_MISC_CH3_STAT_SRC_Pos                           (39U)
#define AHBDMA_MISC_CH3_STAT_SRC_Msk                           (0x1UL << AHBDMA_MISC_CH3_STAT_SRC_Pos)
#define AHBDMA_MISC_CH3_DST_SCA_EN_Pos                         (40U)
#define AHBDMA_MISC_CH3_DST_SCA_EN_Msk                         (0x1UL << AHBDMA_MISC_CH3_DST_SCA_EN_Pos)
#define AHBDMA_MISC_CH3_SRC_GAT_EN_Pos                         (41U)
#define AHBDMA_MISC_CH3_SRC_GAT_EN_Msk                         (0x1UL << AHBDMA_MISC_CH3_SRC_GAT_EN_Pos)
#define AHBDMA_MISC_CH3_LOCK_EN_Pos                            (42U)
#define AHBDMA_MISC_CH3_LOCK_EN_Msk                            (0x1UL << AHBDMA_MISC_CH3_LOCK_EN_Pos)
#define AHBDMA_MISC_CH3_MULTI_BLK_EN_Pos                       (43U)
#define AHBDMA_MISC_CH3_MULTI_BLK_EN_Msk                       (0x1UL << AHBDMA_MISC_CH3_MULTI_BLK_EN_Pos)
#define AHBDMA_MISC_CH3_CTL_WB_EN_Pos                          (44U)
#define AHBDMA_MISC_CH3_CTL_WB_EN_Msk                          (0x1UL << AHBDMA_MISC_CH3_CTL_WB_EN_Pos)
#define AHBDMA_MISC_CH3_HC_LLP_Pos                             (45U)
#define AHBDMA_MISC_CH3_HC_LLP_Msk                             (0x1UL << AHBDMA_MISC_CH3_HC_LLP_Pos)
#define AHBDMA_MISC_CH3_FC_Pos                                 (46U)
#define AHBDMA_MISC_CH3_FC_Msk                                 (0x3UL << AHBDMA_MISC_CH3_FC_Pos)
#define AHBDMA_MISC_CH3_MAX_MULT_SIZE_Pos                      (48U)
#define AHBDMA_MISC_CH3_MAX_MULT_SIZE_Msk                      (0x7UL << AHBDMA_MISC_CH3_MAX_MULT_SIZE_Pos)
#define AHBDMA_MISC_CH3_DMS_Pos                                (51U)
#define AHBDMA_MISC_CH3_DMS_Msk                                (0x7UL << AHBDMA_MISC_CH3_DMS_Pos)
#define AHBDMA_MISC_CH3_LMS_Pos                                (54U)
#define AHBDMA_MISC_CH3_LMS_Msk                                (0x7UL << AHBDMA_MISC_CH3_LMS_Pos)
#define AHBDMA_MISC_CH3_SMS_Pos                                (57U)
#define AHBDMA_MISC_CH3_SMS_Msk                                (0x7UL << AHBDMA_MISC_CH3_SMS_Pos)
#define AHBDMA_MISC_CH3_FIFO_DEPTH_Pos                         (60U)
#define AHBDMA_MISC_CH3_FIFO_DEPTH_Msk                         (0x7UL << AHBDMA_MISC_CH3_FIFO_DEPTH_Pos)
#define AHBDMA_MISC_Rsvd_1_DMA_COMP_PARAMS_4_Pos               (63U)
#define AHBDMA_MISC_Rsvd_1_DMA_COMP_PARAMS_4_Msk               (0x1UL << AHBDMA_MISC_Rsvd_1_DMA_COMP_PARAMS_4_Pos)

/********************  Bits definition for AHB DMAC Component Parameters Register 3 *******************/
#define AHBDMA_MISC_CH2_DTW_Pos                                (0U)
#define AHBDMA_MISC_CH2_DTW_Msk                                (0x7UL << AHBDMA_MISC_CH2_DTW_Pos)
#define AHBDMA_MISC_CH2_STW_Pos                                (3U)
#define AHBDMA_MISC_CH2_STW_Msk                                (0x7UL << AHBDMA_MISC_CH2_STW_Pos)
#define AHBDMA_MISC_CH2_STAT_DST_Pos                           (6U)
#define AHBDMA_MISC_CH2_STAT_DST_Msk                           (0x1UL << AHBDMA_MISC_CH2_STAT_DST_Pos)
#define AHBDMA_MISC_CH2_STAT_SRC_Pos                           (7U)
#define AHBDMA_MISC_CH2_STAT_SRC_Msk                           (0x1UL << AHBDMA_MISC_CH2_STAT_SRC_Pos)
#define AHBDMA_MISC_CH2_DST_SCA_EN_Pos                         (8U)
#define AHBDMA_MISC_CH2_DST_SCA_EN_Msk                         (0x1UL << AHBDMA_MISC_CH2_DST_SCA_EN_Pos)
#define AHBDMA_MISC_CH2_SRC_GAT_EN_Pos                         (9U)
#define AHBDMA_MISC_CH2_SRC_GAT_EN_Msk                         (0x1UL << AHBDMA_MISC_CH2_SRC_GAT_EN_Pos)
#define AHBDMA_MISC_CH2_LOCK_EN_Pos                            (10U)
#define AHBDMA_MISC_CH2_LOCK_EN_Msk                            (0x1UL << AHBDMA_MISC_CH2_LOCK_EN_Pos)
#define AHBDMA_MISC_CH2_MULTI_BLK_EN_Pos                       (11U)
#define AHBDMA_MISC_CH2_MULTI_BLK_EN_Msk                       (0x1UL << AHBDMA_MISC_CH2_MULTI_BLK_EN_Pos)
#define AHBDMA_MISC_CH2_CTL_WB_EN_Pos                          (12U)
#define AHBDMA_MISC_CH2_CTL_WB_EN_Msk                          (0x1UL << AHBDMA_MISC_CH2_CTL_WB_EN_Pos)
#define AHBDMA_MISC_CH2_HC_LLP_Pos                             (13U)
#define AHBDMA_MISC_CH2_HC_LLP_Msk                             (0x1UL << AHBDMA_MISC_CH2_HC_LLP_Pos)
#define AHBDMA_MISC_CH2_FC_Pos                                 (14U)
#define AHBDMA_MISC_CH2_FC_Msk                                 (0x3UL << AHBDMA_MISC_CH2_FC_Pos)
#define AHBDMA_MISC_CH2_MAX_MULT_SIZE_Pos                      (16U)
#define AHBDMA_MISC_CH2_MAX_MULT_SIZE_Msk                      (0x7UL << AHBDMA_MISC_CH2_MAX_MULT_SIZE_Pos)
#define AHBDMA_MISC_CH2_DMS_Pos                                (19U)
#define AHBDMA_MISC_CH2_DMS_Msk                                (0x7UL << AHBDMA_MISC_CH2_DMS_Pos)
#define AHBDMA_MISC_CH2_LMS_Pos                                (22U)
#define AHBDMA_MISC_CH2_LMS_Msk                                (0x7UL << AHBDMA_MISC_CH2_LMS_Pos)
#define AHBDMA_MISC_CH2_SMS_Pos                                (25U)
#define AHBDMA_MISC_CH2_SMS_Msk                                (0x7UL << AHBDMA_MISC_CH2_SMS_Pos)
#define AHBDMA_MISC_CH2_FIFO_DEPTH_Pos                         (28U)
#define AHBDMA_MISC_CH2_FIFO_DEPTH_Msk                         (0x7UL << AHBDMA_MISC_CH2_FIFO_DEPTH_Pos)
#define AHBDMA_MISC_Rsvd_DMA_COMP_PARAMS_3_Pos                 (31U)
#define AHBDMA_MISC_Rsvd_DMA_COMP_PARAMS_3_Msk                 (0x1UL << AHBDMA_MISC_Rsvd_DMA_COMP_PARAMS_3_Pos)
#define AHBDMA_MISC_CH1_DTW_Pos                                (32U)
#define AHBDMA_MISC_CH1_DTW_Msk                                (0x7UL << AHBDMA_MISC_CH1_DTW_Pos)
#define AHBDMA_MISC_CH1_STW_Pos                                (35U)
#define AHBDMA_MISC_CH1_STW_Msk                                (0x7UL << AHBDMA_MISC_CH1_STW_Pos)
#define AHBDMA_MISC_CH1_STAT_DST_Pos                           (38U)
#define AHBDMA_MISC_CH1_STAT_DST_Msk                           (0x1UL << AHBDMA_MISC_CH1_STAT_DST_Pos)
#define AHBDMA_MISC_CH1_STAT_SRC_Pos                           (39U)
#define AHBDMA_MISC_CH1_STAT_SRC_Msk                           (0x1UL << AHBDMA_MISC_CH1_STAT_SRC_Pos)
#define AHBDMA_MISC_CH1_DST_SCA_EN_Pos                         (40U)
#define AHBDMA_MISC_CH1_DST_SCA_EN_Msk                         (0x1UL << AHBDMA_MISC_CH1_DST_SCA_EN_Pos)
#define AHBDMA_MISC_CH1_SRC_GAT_EN_Pos                         (41U)
#define AHBDMA_MISC_CH1_SRC_GAT_EN_Msk                         (0x1UL << AHBDMA_MISC_CH1_SRC_GAT_EN_Pos)
#define AHBDMA_MISC_CH1_LOCK_EN_Pos                            (42U)
#define AHBDMA_MISC_CH1_LOCK_EN_Msk                            (0x1UL << AHBDMA_MISC_CH1_LOCK_EN_Pos)
#define AHBDMA_MISC_CH1_MULTI_BLK_EN_Pos                       (43U)
#define AHBDMA_MISC_CH1_MULTI_BLK_EN_Msk                       (0x1UL << AHBDMA_MISC_CH1_MULTI_BLK_EN_Pos)
#define AHBDMA_MISC_CH1_CTL_WB_EN_Pos                          (44U)
#define AHBDMA_MISC_CH1_CTL_WB_EN_Msk                          (0x1UL << AHBDMA_MISC_CH1_CTL_WB_EN_Pos)
#define AHBDMA_MISC_CH1_HC_LLP_Pos                             (45U)
#define AHBDMA_MISC_CH1_HC_LLP_Msk                             (0x1UL << AHBDMA_MISC_CH1_HC_LLP_Pos)
#define AHBDMA_MISC_CH1_FC_Pos                                 (46U)
#define AHBDMA_MISC_CH1_FC_Msk                                 (0x3UL << AHBDMA_MISC_CH1_FC_Pos)
#define AHBDMA_MISC_CH1_MAX_MULT_SIZE_Pos                      (48U)
#define AHBDMA_MISC_CH1_MAX_MULT_SIZE_Msk                      (0x7UL << AHBDMA_MISC_CH1_MAX_MULT_SIZE_Pos)
#define AHBDMA_MISC_CH1_DMS_Pos                                (51U)
#define AHBDMA_MISC_CH1_DMS_Msk                                (0x7UL << AHBDMA_MISC_CH1_DMS_Pos)
#define AHBDMA_MISC_CH1_LMS_Pos                                (54U)
#define AHBDMA_MISC_CH1_LMS_Msk                                (0x7UL << AHBDMA_MISC_CH1_LMS_Pos)
#define AHBDMA_MISC_CH1_SMS_Pos                                (57U)
#define AHBDMA_MISC_CH1_SMS_Msk                                (0x7UL << AHBDMA_MISC_CH1_SMS_Pos)
#define AHBDMA_MISC_CH1_FIFO_DEPTH_Pos                         (60U)
#define AHBDMA_MISC_CH1_FIFO_DEPTH_Msk                         (0x7UL << AHBDMA_MISC_CH1_FIFO_DEPTH_Pos)
#define AHBDMA_MISC_Rsvd_1_DMA_COMP_PARAMS_3_Pos               (63U)
#define AHBDMA_MISC_Rsvd_1_DMA_COMP_PARAMS_3_Msk               (0x1UL << AHBDMA_MISC_Rsvd_1_DMA_COMP_PARAMS_3_Pos)

/********************  Bits definition for AHB DMAC Component Parameters Register 2 *******************/
#define AHBDMA_MISC_CH0_DTW_Pos                                      (0U)
#define AHBDMA_MISC_CH0_DTW_Msk                                      (0x7UL << AHBDMA_MISC_CH0_DTW_Pos)
#define AHBDMA_MISC_CH0_STW_Pos                                      (3U)
#define AHBDMA_MISC_CH0_STW_Msk                                      (0x7UL << AHBDMA_MISC_CH0_STW_Pos)
#define AHBDMA_MISC_CH0_STAT_DST_Pos                                 (6U)
#define AHBDMA_MISC_CH0_STAT_DST_Msk                                 (0x1UL << AHBDMA_MISC_CH0_STAT_DST_Pos)
#define AHBDMA_MISC_CH0_STAT_SRC_Pos                                 (7U)
#define AHBDMA_MISC_CH0_STAT_SRC_Msk                                 (0x1UL << AHBDMA_MISC_CH0_STAT_SRC_Pos)
#define AHBDMA_MISC_CH0_DST_SCA_EN_Pos                               (8U)
#define AHBDMA_MISC_CH0_DST_SCA_EN_Msk                               (0x1UL << AHBDMA_MISC_CH0_DST_SCA_EN_Pos)
#define AHBDMA_MISC_CH0_SRC_GAT_EN_Pos                               (9U)
#define AHBDMA_MISC_CH0_SRC_GAT_EN_Msk                               (0x1UL << AHBDMA_MISC_CH0_SRC_GAT_EN_Pos)
#define AHBDMA_MISC_CH0_LOCK_EN_Pos                                  (10U)
#define AHBDMA_MISC_CH0_LOCK_EN_Msk                                  (0x1UL << AHBDMA_MISC_CH0_LOCK_EN_Pos)
#define AHBDMA_MISC_CH0_MULTI_BLK_EN_Pos                             (11U)
#define AHBDMA_MISC_CH0_MULTI_BLK_EN_Msk                             (0x1UL << AHBDMA_MISC_CH0_MULTI_BLK_EN_Pos)
#define AHBDMA_MISC_CH0_CTL_WB_EN_Pos                                (12U)
#define AHBDMA_MISC_CH0_CTL_WB_EN_Msk                                (0x1UL << AHBDMA_MISC_CH0_CTL_WB_EN_Pos)
#define AHBDMA_MISC_CH0_HC_LLP_Pos                                   (13U)
#define AHBDMA_MISC_CH0_HC_LLP_Msk                                   (0x1UL << AHBDMA_MISC_CH0_HC_LLP_Pos)
#define AHBDMA_MISC_CH0_FC_Pos                                       (14U)
#define AHBDMA_MISC_CH0_FC_Msk                                       (0x3UL << AHBDMA_MISC_CH0_FC_Pos)
#define AHBDMA_MISC_CH0_MAX_MULT_SIZE_Pos                            (16U)
#define AHBDMA_MISC_CH0_MAX_MULT_SIZE_Msk                            (0x7UL << AHBDMA_MISC_CH0_MAX_MULT_SIZE_Pos)
#define AHBDMA_MISC_CH0_DMS_Pos                                      (19U)
#define AHBDMA_MISC_CH0_DMS_Msk                                      (0x1UL << AHBDMA_MISC_CH0_DMS_Pos)
#define AHBDMA_MISC_CH0_LMS_Pos                                      (22U)
#define AHBDMA_MISC_CH0_LMS_Msk                                      (0x7UL << AHBDMA_MISC_CH0_LMS_Pos)
#define AHBDMA_MISC_CH0_SMS_Pos                                      (25U)
#define AHBDMA_MISC_CH0_SMS_Msk                                      (0x7UL << AHBDMA_MISC_CH0_SMS_Pos)
#define AHBDMA_MISC_CH0_FIFO_DEPTH_Pos                               (28U)
#define AHBDMA_MISC_CH0_FIFO_DEPTH_Msk                               (0x7UL << AHBDMA_MISC_CH0_FIFO_DEPTH_Pos)
#define AHBDMA_MISC_Rsvd_DMA_COMP_PARAMS_2_Pos                       (31U)
#define AHBDMA_MISC_Rsvd_DMA_COMP_PARAMS_2_Msk                       (0x1UL << AHBDMA_MISC_Rsvd_DMA_COMP_PARAMS_2_Pos)
#define AHBDMA_MISC_CHO_MULTI_BLK_TYPE_Pos                           (32U)
#define AHBDMA_MISC_CHO_MULTI_BLK_TYPE_Msk                           (0xFUL << AHBDMA_MISC_CHO_MULTI_BLK_TYPE_Pos)
#define AHBDMA_MISC_CH1_MULTI_BLK_TYPE_Pos                           (36U)
#define AHBDMA_MISC_CH1_MULTI_BLK_TYPE_Msk                           (0xFUL << AHBDMA_MISC_CH1_MULTI_BLK_TYPE_Pos)
#define AHBDMA_MISC_CH2_MULTI_BLK_TYPE_Pos                           (40U)
#define AHBDMA_MISC_CH2_MULTI_BLK_TYPE_Msk                           (0xFUL << AHBDMA_MISC_CH2_MULTI_BLK_TYPE_Pos)
#define AHBDMA_MISC_CH3_MULTI_BLK_TYPE_Pos                           (44U)
#define AHBDMA_MISC_CH3_MULTI_BLK_TYPE_Msk                           (0xFUL << AHBDMA_MISC_CH3_MULTI_BLK_TYPE_Pos)
#define AHBDMA_MISC_CH4_MULTI_BLK_TYPE_Pos                           (48U)
#define AHBDMA_MISC_CH4_MULTI_BLK_TYPE_Msk                           (0xFUL << AHBDMA_MISC_CH4_MULTI_BLK_TYPE_Pos)
#define AHBDMA_MISC_CH5_MULTI_BLK_TYPE_Pos                           (52U)
#define AHBDMA_MISC_CH5_MULTI_BLK_TYPE_Msk                           (0xFUL << AHBDMA_MISC_CH5_MULTI_BLK_TYPE_Pos)
#define AHBDMA_MISC_CH6_MULTI_BLK_TYPE_Pos                           (56U)
#define AHBDMA_MISC_CH6_MULTI_BLK_TYPE_Msk                           (0xFUL << AHBDMA_MISC_CH6_MULTI_BLK_TYPE_Pos)
#define AHBDMA_MISC_CH7_MULTI_BLK_TYPE_Pos                           (60U)
#define AHBDMA_MISC_CH7_MULTI_BLK_TYPE_Msk                           (0xFUL << AHBDMA_MISC_CH7_MULTI_BLK_TYPE_Pos)

/********************  Bits definition for AHB DMAC Component Parameters Register 1 *******************/
#define AHBDMA_MISC_CHO_MAX_BLK_SIZE_Pos                        (0)
#define AHBDMA_MISC_CHO_MAX_BLK_SIZE_Msk                        (0xFUL << AHBDMA_MISC_CHO_MAX_BLK_SIZE_Pos)
#define AHBDMA_MISC_CH1_MAX_BLK_SIZE_Pos                        (4)
#define AHBDMA_MISC_CH1_MAX_BLK_SIZE_Msk                        (0xFUL << AHBDMA_MISC_CH1_MAX_BLK_SIZE_Pos)
#define AHBDMA_MISC_CH2_MAX_BLK_SIZE_Pos                        (8)
#define AHBDMA_MISC_CH2_MAX_BLK_SIZE_Msk                        (0xFUL << AHBDMA_MISC_CH2_MAX_BLK_SIZE_Pos)
#define AHBDMA_MISC_CH3_MAX_BLK_SIZE_Pos                        (12)
#define AHBDMA_MISC_CH3_MAX_BLK_SIZE_Msk                        (0xFUL << AHBDMA_MISC_CH3_MAX_BLK_SIZE_Pos)
#define AHBDMA_MISC_CH4_MAX_BLK_SIZE_Pos                        (16)
#define AHBDMA_MISC_CH4_MAX_BLK_SIZE_Msk                        (0xFUL << AHBDMA_MISC_CH4_MAX_BLK_SIZE_Pos)
#define AHBDMA_MISC_CH5_MAX_BLK_SIZE_Pos                        (20)
#define AHBDMA_MISC_CH5_MAX_BLK_SIZE_Msk                        (0xFUL << AHBDMA_MISC_CH5_MAX_BLK_SIZE_Pos)
#define AHBDMA_MISC_CH6_MAX_BLK_SIZE_Pos                        (24)
#define AHBDMA_MISC_CH6_MAX_BLK_SIZE_Msk                        (0xFUL << AHBDMA_MISC_CH6_MAX_BLK_SIZE_Pos)
#define AHBDMA_MISC_CH7_MAX_BLK_SIZE_Pos                        (28)
#define AHBDMA_MISC_CH7_MAX_BLK_SIZE_Msk                        (0xFUL << AHBDMA_MISC_CH7_MAX_BLK_SIZE_Pos)
#define AHBDMA_MISC_BIG_ENDIAN_Pos                              (32)
#define AHBDMA_MISC_BIG_ENDIAN_Msk                              (0x1UL << AHBDMA_MISC_BIG_ENDIAN_Pos)
#define AHBDMA_MISC_INTR_IO_Pos                                 (33)
#define AHBDMA_MISC_INTR_IO_Msk                                 (0x3UL << AHBDMA_MISC_INTR_IO_Pos)
#define AHBDMA_MISC_MAX_ABRST_Pos                               (35)
#define AHBDMA_MISC_MAX_ABRST_Msk                               (0x1UL << AHBDMA_MISC_MAX_ABRST_Pos)
#define AHBDMA_MISC_Rsvd_DMA_COMP_PARAMS_1_Pos                  (36)
#define AHBDMA_MISC_Rsvd_DMA_COMP_PARAMS_1_Msk                  (0xFUL << AHBDMA_MISC_Rsvd_DMA_COMP_PARAMS_1_Pos)
#define AHBDMA_MISC_NUM_CHANNELS_Pos                            (40)
#define AHBDMA_MISC_NUM_CHANNELS_Msk                            (0x7UL << AHBDMA_MISC_NUM_CHANNELS_Pos)
#define AHBDMA_MISC_NUM_MASTER_INT_Pos                          (43)
#define AHBDMA_MISC_NUM_MASTER_INT_Msk                          (0x3UL << AHBDMA_MISC_NUM_MASTER_INT_Pos)
#define AHBDMA_MISC_S_HDATA_WIDTH_Pos                           (45)
#define AHBDMA_MISC_S_HDATA_WIDTH_Msk                           (0x3UL << AHBDMA_MISC_S_HDATA_WIDTH_Pos)
#define AHBDMA_MISC_M4_HDATA_WIDTH_Pos                          (47)
#define AHBDMA_MISC_M4_HDATA_WIDTH_Msk                          (0x3UL << AHBDMA_MISC_M4_HDATA_WIDTH_Pos)
#define AHBDMA_MISC_M3_HDATA_WIDTH_Pos                          (49)
#define AHBDMA_MISC_M3_HDATA_WIDTH_Msk                          (0x3UL << AHBDMA_MISC_M3_HDATA_WIDTH_Pos)
#define AHBDMA_MISC_M2_HDATA_WIDTH_Pos                          (51)
#define AHBDMA_MISC_M2_HDATA_WIDTH_Msk                          (0x3UL << AHBDMA_MISC_M2_HDATA_WIDTH_Pos)
#define AHBDMA_MISC_M1_HDATA_WIDTH_Pos                          (53)
#define AHBDMA_MISC_M1_HDATA_WIDTH_Msk                          (0x3UL << AHBDMA_MISC_M1_HDATA_WIDTH_Pos)
#define AHBDMA_MISC_NUM_HS_INT_Pos                              (55)
#define AHBDMA_MISC_NUM_HS_INT_Msk                              (0x1FUL << AHBDMA_MISC_NUM_HS_INT_Pos)
#define AHBDMA_MISC_ADD_ENCODED_PARAMS_Pos                      (60)
#define AHBDMA_MISC_ADD_ENCODED_PARAMS_Msk                      (0x1UL << AHBDMA_MISC_ADD_ENCODED_PARAMS_Pos)
#define AHBDMA_MISC_STATIC_ENDIAN_SELECT_Pos                    (61)
#define AHBDMA_MISC_STATIC_ENDIAN_SELECT_Msk                    (0x1UL << AHBDMA_MISC_STATIC_ENDIAN_SELECT_Pos)
#define AHBDMA_MISC_Rsvd_1_DMA_COMP_PARAMS_1_Pos                (62)
#define AHBDMA_MISC_Rsvd_1_DMA_COMP_PARAMS_1_Msk                (0x3UL << AHBDMA_MISC_Rsvd_1_DMA_COMP_PARAMS_1_Pos)

/********************  Bits definition for AHB DMAC DMA Component ID Register *******************/
#define AHBDMA_MISC_COMP_TYPE_Pos                            (0U)
#define AHBDMA_MISC_COMP_TYPE_Msk                            (0xFFFFFFFFUL << AHBDMA_MISC_COMP_TYPE_Pos)

/** @addtogroup ET6001_Driver
 * @{
 */

/** @addtogroup AHBDMA
 * @{
 */

/* AHBDMA channel number */
#define AHBDMA_NUM_CHANNELS         (8)

/* AHBDMA error channel number */
#define AHBDMA_CH_ERR               (0xFFFFFFFFU)

/* AHBDMA channel select */
#define AHBDMA_CH_0                 (0U)
#define AHBDMA_CH_1                 (1U)
#define AHBDMA_CH_2                 (2U)
#define AHBDMA_CH_3                 (3U)
#define AHBDMA_CH_4                 (4U)
#define AHBDMA_CH_5                 (5U)
#define AHBDMA_CH_6                 (6U)
#define AHBDMA_CH_7                 (7U)

/* AHBDMA channel max block transfer size */
#define AHBDMA_MAX_BLOCK_TR_SIZE    (4096U - 1U)

/* AHBDMA channel transfer width */
/* Source or Destination Transfer Width is 8 bits */
#define AHBDMA_BITS_8                  0U
/* Source or Destination Transfer Width is 16 bits */
#define AHBDMA_BITS_16                 1U
/* Source or Destination Transfer Width is 32 bits */
#define AHBDMA_BITS_32                 2U

/* AHBDMA channel address increment direction */
#define AHBDMA_INCREMENTAL             0U
#define AHBDMA_DECREMENTAL             1U
#define AHBDMA_FIXED                   2U

/* AHBDMA channel burst transfer items number */
#define AHBDMA_BURST_DATA_ITEMS_1      (0U)
#define AHBDMA_BURST_DATA_ITEMS_4      (1U)
#define AHBDMA_BURST_DATA_ITEMS_8      (2U)
#define AHBDMA_BURST_DATA_ITEMS_16     (3U)
#define AHBDMA_BURST_DATA_ITEMS_32     (4U)
#define AHBDMA_BURST_DATA_ITEMS_64     (5U)
#define AHBDMA_BURST_DATA_ITEMS_128    (6U)
#define AHBDMA_BURST_DATA_ITEMS_256    (7U)

/* AHBDMA channel transfer type */
/* Transfer Type is memory to memory and Flow Controller is DMAC */
#define AHBDMA_MEM_TO_MEM       (0U)
/* Transfer Type is memory to peripheral and Flow Controller is DMAC*/
#define AHBDMA_MEM_TO_PER       (1U)
/* Transfer Type is peripheral to memory and Flow Controller is DMAC*/
#define AHBDMA_PER_TO_MEM       (2U)
/* Transfer Type is peripheral to peripheral and Flow Controller is DMAC*/
#define AHBDMA_PER_TO_PER       (3U)

/* AHBDMA channel transfer channel priority */
#define AHBDMA_CH_PRIORITY_0    (0U) /* The lowest priority */
#define AHBDMA_CH_PRIORITY_1    (1U)
#define AHBDMA_CH_PRIORITY_2    (2U)
#define AHBDMA_CH_PRIORITY_3    (3U)
#define AHBDMA_CH_PRIORITY_4    (4U)
#define AHBDMA_CH_PRIORITY_5    (5U)
#define AHBDMA_CH_PRIORITY_6    (6U)
#define AHBDMA_CH_PRIORITY_7    (7U) /* The highest priority */

/* AHBDMA channel FIFO mode select */
/* Space/data available for single AHB transfer of the specified transfer width */
#define AHBDMA_FIFO_SINGLE        (0U)

/**
 * Data available is greater than or
 * equal to half the fifo depth for destination transfers and
 * space available is greater than half the fifo depth for
 * source transfers. the exceptions are at the end of a burst
 * transaction request or at the end of a block transfer.
 */
#define AHBDMA_FIFO_HALF_DEPTH    (1U)

/* AHBDMA interrupt mask */
#define AHBDMA_IT_TFR_MASK        (1U << 0U)
#define AHBDMA_IT_BLOCK_MASK      (1U << 1U)
#define AHBDMA_IT_SRCTRAN_MASK    (1U << 2U)
#define AHBDMA_IT_DSTTRAN_MASK    (1U << 3U)
#define AHBDMA_IT_ERR_MASK        (1U << 4U)

/* AHBDMA channel memory hardware interface */
#define AHBDMA_IF_MEM             (0U)

/* AHBDMA0 channel hardware interface */
#define AHBDMA0_IF_DAC0           (0U)
#define AHBDMA0_IF_DAC1           (1U)
#define AHBDMA0_IF_SRPWM0         (2U)
#define AHBDMA0_IF_SRPWM1         (3U)
#define AHBDMA0_IF_SRPWM2         (4U)
#define AHBDMA0_IF_SRPWM3         (5U)
#define AHBDMA0_IF_ADC0_CH2       (6U)
#define AHBDMA0_IF_ADC0_CH3       (7U)
#define AHBDMA0_IF_ADC1_CH2       (8U)
#define AHBDMA0_IF_ADC1_CH3       (9U)
#define AHBDMA0_IF_ADC2_CH2       (10U)
#define AHBDMA0_IF_ADC2_CH3       (11U)
#define AHBDMA0_IF_ACMP0_A        (12U)
#define AHBDMA0_IF_ACMP0_B        (13U)
#define AHBDMA0_IF_ACMP1_A        (14U)
#define AHBDMA0_IF_ACMP1_B        (15U)

/* AHBDMA1 channel hardware interface */
#define AHBDMA1_IF_REV0           (0U)
#define AHBDMA1_IF_REV1           (1U)
#define AHBDMA1_IF_ETIMER0        (2U)
#define AHBDMA1_IF_ETIMER1        (3U)
#define AHBDMA1_IF_ETIMER2        (4U)
#define AHBDMA1_IF_ETIMER3        (5U)
#define AHBDMA1_IF_ADC0_CH0       (6U)
#define AHBDMA1_IF_ADC0_CH1       (7U)
#define AHBDMA1_IF_ADC1_CH0       (8U)
#define AHBDMA1_IF_ADC1_CH1       (9U)
#define AHBDMA1_IF_ADC2_CH0       (10U)
#define AHBDMA1_IF_ADC2_CH1       (11U)
#define AHBDMA1_IF_ACMP2_A        (12U)
#define AHBDMA1_IF_ACMP2_B        (13U)
#define AHBDMA1_IF_ACMP3_A        (14U)
#define AHBDMA1_IF_ACMP3_B        (15U)

/* AHBDMA channel multi trans type */
#define AHBDMA_CONTIGUOUS         0U
#define AHBDMA_RELOAD             1U
#define AHBDMA_LINKED_LIST        2U

/**
 * @brief AHBDMA channel init structure
 *
 */
typedef struct __PACKED
{
    uint32_t      sar;                          /* source address  */
    uint32_t      dar;                          /* destination address */
    uint8_t       srcTrWidth;                   /* source transfer width */
    uint8_t       dstTrWidth;                   /* destination transfer width */
    uint8_t       srcAddressInc;                /* source address incremental direction */
    uint8_t       dstAddressInc;                /* destination address incremental direction */
    uint8_t       srcBurstDataItemsNum;         /* source burst transfer data items number */
    uint8_t       dstBurstDataItemsNum;         /* destination burst transfer data items number */
    uint8_t       tfrType;                      /* transfer type in channel */
    ControlStatus dstLLPEn;                     /* destination LLP transfer enable or disable */
    ControlStatus srcLLPEn;                     /* source LLP transfer enable or disable */
    uint16_t      blkTfrSize;                   /* block transfer size */
    ControlStatus wbDoneEn;                     /* write back when transfer is done */
    uint8_t       prior;                        /* priority select */
    ControlStatus srcReloadEn;                  /* destination reload transfer enable or di */
    ControlStatus dstReloadEn;                  /* source reload transfer enable or disable */
    uint8_t       fifoMode;                     /* fifo mode in transfer */
    uint8_t       srcPer;                       /* source address DMA interface */
    uint8_t       dstPer;                       /* destination address DMA interface */
    uint32_t      llp;                          /* link-list pointer */
    ControlStatus srcGatherEn;                  /* source gather transfer enable or disable */
    uint32_t      srcGatherCount;               /* source gather transfer count value */
    uint32_t      srcGatherInterval;            /* source gather transfer interval value */
    ControlStatus dstScatterEn;                 /* destination scatter transfer enable or disable */
    uint32_t      dstScatterCount;              /* destination scatter transfer count value */
    uint32_t      dstScatterInterval;           /* destination scatter transfer interval value */
} AHBDMA_Ch_Init_TypeDef;

/**
 * @brief AHBDMA LLI register structure
 *
 */
typedef struct
{
    uint32_t SAR;               /* store source address register */
    uint32_t DAR;               /* store destination address register */
    uint32_t LLP;               /* store link-list pointer register */
    uint32_t CTL_L;             /* store transfer control low 32 register */
    uint32_t CTL_H;             /* store transfer control high 32 register */
    uint32_t SSTAT;             /* store source status register */
    uint32_t DSTAT;             /* store destination status register */
} AHBDMA_LLI_TypeDef;

/**
 * @brief AHBDMA LLI init structure, including all parameters to fill LLI register structure.
 * member <intEn> is added to control interrupt.
 *
 */
typedef struct
{
    uint32_t      sar;                               /* source address  */
    uint32_t      dar;                               /* destination address */
    ControlStatus intEn;                             /* interrupt enable or disable */
    uint8_t       srcTrWidth;                        /* source transfer width */
    uint8_t       dstTrWidth;                        /* destination transfer width */
    uint8_t       srcAddressInc;                     /* source address incremental direction */
    uint8_t       dstAddressInc;                     /* destination address incremental direction */
    uint8_t       srcBurstDataItemsNum;              /* source burst transfer data items number */
    uint8_t       dstBurstDataItemsNum;              /* destination burst transfer data items number */
    ControlStatus dstScatterEn;                      /* source gather transfer enable or disable */
    ControlStatus srcGatherEn;                       /* destination scatter transfer enable or disable */
    uint8_t       tfrType;                           /* transfer type in channel */
    ControlStatus dstLLPEn;                          /* destination LLP transfer enable or disable */
    ControlStatus srcLLPEn;                          /* source LLP transfer enable or disable */
    uint16_t      blkTfrSize;                        /* block transfer size */
    ControlStatus wbDoneEn;                          /* write back when transfer is done */
    uint32_t      llp;                               /* link-list pointer */
} AHBDMA_LLI_Init_TypeDef;

DRV_StatusTypeDef AHBDMA_Enable(AHBDMA_TypeDef *AHBDMAx);
DRV_StatusTypeDef AHBDMA_Disable(AHBDMA_TypeDef *AHBDMAx);
void AHBDMA_ChInit(AHBDMA_TypeDef *AHBDMAx, const AHBDMA_Ch_Init_TypeDef *init, uint32_t ch);
DRV_StatusTypeDef AHBDMA_ChDeInit(AHBDMA_TypeDef *AHBDMAx, uint32_t ch);
void AHBDMA_ChStructInit(AHBDMA_Ch_Init_TypeDef *init);
DRV_StatusTypeDef AHBDMA_ChEnable(AHBDMA_TypeDef *AHBDMAx, uint32_t ch);
DRV_StatusTypeDef AHBDMA_ChDisable(AHBDMA_TypeDef *AHBDMAx, uint32_t ch);
void AHBDMA_ChSuspend(AHBDMA_TypeDef *AHBDMAx, uint32_t ch);
void AHBDMA_ChResume(AHBDMA_TypeDef *AHBDMAx, uint32_t ch);
uint32_t AHBDMA_FindFreeChannel(AHBDMA_TypeDef *AHBDMAx);
bool AHBDMA_IsChannelFree(AHBDMA_TypeDef *AHBDMAx, uint32_t ch);
bool AHBDMA_IsChannelFifoEmpty(AHBDMA_TypeDef *AHBDMAx, uint32_t ch);
DRV_StatusTypeDef AHBDMA_M2MDefaultSet(AHBDMA_Ch_Init_TypeDef *init, uint32_t srcAddress, uint32_t dstAddress,
                                       uint32_t size);
DRV_StatusTypeDef AHBDMA_M2PDefaultSet(AHBDMA_Ch_Init_TypeDef *init, uint32_t srcAddress, uint32_t dstAddress,
                                       uint32_t size, uint8_t dstPeripIF);
DRV_StatusTypeDef AHBDMA_P2MDefaultSet(AHBDMA_Ch_Init_TypeDef *init, uint32_t srcAddress, uint32_t dstAddress,
                                       uint32_t size, uint8_t srcPeripIF);
DRV_StatusTypeDef AHBDMA_P2PDefaultSet(AHBDMA_Ch_Init_TypeDef *init, uint32_t srcAddress, uint32_t dstAddress,
                                       uint32_t size, uint8_t srcPeripIF, uint8_t dstPeripIF);
DRV_StatusTypeDef AHBDMA_MultiBlockSet(AHBDMA_Ch_Init_TypeDef *init, uint8_t sarUpdateMethod,
                                       uint8_t darUpdateMethod, uint32_t llp);
void AHBDMA_SourceGatherSet(AHBDMA_Ch_Init_TypeDef *init, uint32_t gatherInterval, uint32_t gatherCount,
                            ControlStatus status);
void AHBDMA_DestinationScatterSet(AHBDMA_Ch_Init_TypeDef *init, uint32_t scatterInterval,
                                  uint32_t scatterCount, ControlStatus status);
void AHBDMA_LLI_Init(AHBDMA_LLI_TypeDef *lli, const AHBDMA_LLI_Init_TypeDef *init, bool isLastLLI, uint32_t nextLLP);
void AHBDMA_LLI_StructInit(AHBDMA_LLI_Init_TypeDef *init);
DRV_StatusTypeDef AHBDMA_LLI_M2MDefaultSet(AHBDMA_LLI_Init_TypeDef *init, uint32_t srcAddress, uint32_t dstAddress,
                                           uint32_t size, ControlStatus srcLLIUpdate, ControlStatus dstLLIUpdate);
DRV_StatusTypeDef AHBDMA_LLI_M2PDefaultSet(AHBDMA_LLI_Init_TypeDef *init, uint32_t srcAddress, uint32_t dstAddress,
                                           uint32_t size, ControlStatus srcLLIUpdate, ControlStatus dstLLIUpdate);
DRV_StatusTypeDef AHBDMA_LLI_P2MDefaultSet(AHBDMA_LLI_Init_TypeDef *init, uint32_t srcAddress, uint32_t dstAddress,
                                           uint32_t size, ControlStatus srcLLIUpdate, ControlStatus dstLLIUpdate);
DRV_StatusTypeDef AHBDMA_LLI_P2PDefaultSet(AHBDMA_LLI_Init_TypeDef *init, uint32_t srcAddress, uint32_t dstAddress,
                                           uint32_t size, ControlStatus srcLLIUpdate, ControlStatus dstLLIUpdate);
void AHBDMA_ChITEnable(AHBDMA_TypeDef *AHBDMAx, uint32_t ch, uint32_t ITMasks);
void AHBDMA_ChITDisable(AHBDMA_TypeDef *AHBDMAx, uint32_t ch, uint32_t ITMasks);
uint32_t AHBDMA_TfrITChMaskGet(AHBDMA_TypeDef *AHBDMAx);
uint32_t AHBDMA_BlockITChMaskGet(AHBDMA_TypeDef *AHBDMAx);
uint32_t AHBDMA_SrctranITChMaskGet(AHBDMA_TypeDef *AHBDMAx);
uint32_t AHBDMA_DsttranITChMaskGet(AHBDMA_TypeDef *AHBDMAx);
uint32_t AHBDMA_ErrITChMaskGet(AHBDMA_TypeDef *AHBDMAx);
void AHBDMA_ChITClear(AHBDMA_TypeDef *AHBDMAx, uint32_t ch, uint32_t ITMasks);

#ifdef __cplusplus
}
#endif

#endif /* __DW_AHBDMA_H */
